3-DIMENSIONAL or 3D INTEGRATED CIRCUITS
For the growth of semiconductor technology, three-dimensional integration of microsystems and subsystems has become essential. 3D integration needs a better knowledge of several interconnected systems overlapping each other. Vertical development greatly improves the functionality of the 3D IC technology and also reduces the complexity of the design exponentially. The integrated three-dimensional circuit (3D-IC) includes two or more layers of vertically stacked active electronic components. Stacking of conventional 2D chips helps improve the inter-chip bandwidth resulting in faster data exchange. This helps in significantly improving the performance of the overall system. 3D integration can also result in overall system energy savings due to reduced inter-chip communication overheads, increased integration densities leading to improved performance and functionality and co-integration of heterogeneous components. 3D integration is being touted as a significant approach to counter the slowing of Moore’s law.
The improvements in performance as well as heterogeneity which can enable co- integration of image sensors and processors can have a significant impact on future computer vision systems. 3D Integrated Circuits and Systems Design covers all 3D implementation elements, including 3D circuit and system design, new processes and simulation techniques, alternative 3D circuit and system communication schemes, application of new 3D device parts, and heat problems to reduce energy dissipation and improve 3D system efficiency. The figure shown below indicates a stacked 3D-IC with four levels. Each active layer in the 3D-IC includes functional units like processor cores and memories, or heterogeneous devices like analog RF circuits, sensors, etc. Through-silicon-vias (TSVs) are inserted into the 3D-IC to produce signal / power / ground between distinct levels and enable communication between distinct layers of devices.
Classification of 3D Integrated Circuits
There are different manufacturing technologies for stacked 3D-ICs:
- Wafer on Wafer: The electronic components are firstly built on two or more wafers. The wafers are then bounded together.
- Die on Wafer: The electronic components are built on two different wafers. One wafer is diced and then stacked on the other wafer.
- Die on Die: The electronic components are built on multiple dies; these dies are then bonded together
Despite the advantages, the 3D-IC also brings forth new challenges:
- Design Challenges: The third dimension brings forth an additional control variable during the design of the electronic system. Conventional design tools are geared towards 2D technology. New EDA tools for 3D- ICs are necessary.
- Thermal Issues: In 3D-ICs, since several layers of electronic components that dissipate power are stacked vertically, the power density is usually higher than 2D- ICs, leading to potential thermal issues. In addition, the oxide layer’s thermal conductivity (which is between silicon layers) is small and would therefore decrease the transfer of heat to the environment. This exacerbates the 3D-IC heat issues. New 3D-IC cooling solutions may be needed.
- TSV Induced Overheads: 3D-ICs incorporate thousands of TSVs for interlayer communication as well as delivery of power/ground. These TSVs are causing additional overhead space. Due to the heat expansion mismatch between silicon and TSV filling material, TSVs also cause thermal-mechanical stress. The thermal stress causes potential reliability problems, such as cracking, and also timing violations since transistor delay will be influenced by thermal stress.
- Cross talk between Layers: Coupling might occur between the top layer metal wires and the device on the active layer above it. Furthermore, in heterogeneous integration, the RF Signal might influence the logic and memory in other layers.
Overall, 3D Integration is a significant development which has a major impact on the design of future electronic systems
Cooling Methods in 3D Integrated Circuits
Microchannels can be integrated into a 3D IC chip stack as a cooling interlayer. These layers can be placed between each of the chips of the IC, or after each of the two or more chips. The challenge of microchannel cooling is to integrate it with TSVs. The TSVs can only be located at the walls of the channel, and a large number of closely spaced microchannels are therefore desired. The desirable channel sizes in combination with the need for short TSV distances, tend to be brief and narrow microchannels. Such channels will produce high heat transfer efficiency due to small hydraulic diameters, but the pressure of the coolant stream falls through these channels becomes prohibitively excessive. Microchannels are generally classified in the range of 10–200μm as channels with a minimum element. In the case of conduction cooling, either the microchannels are placed directly in the silicon substratum or etched or machined in a separate silicon or copper chip connected to the back of the IC chip. These passages can also be etched between the interlayer in 3D ICs. A microchannel-cooled 3-layer 3D IC structure can also etch these passages between the interlayer in 3D ICs. Figure 5.1 shows a schematic representation of a 3D IC frame with a microchannel-cooled 3-layer. Microchannels can be used in single and two-phase (evaporative) phases.
- 3D Integrated Circuits: http://www.monolithic3d.com/3d-ic-edge1.html